FPGA design services
RTL, verification, high-speed interfaces and timing closure for AMD FPGAs and adaptive SoCs.
From one AXI block to a complete design running on your board, delivered through our fixed-price packages with a written scope before work starts.
From specification to a bitstream that closes timing
FPGA design is more than RTL that simulates. The logic has to cross clock domains safely, meet timing on the real part, talk to DDR, PCIe or Ethernet at full rate, and come up on a board that may be new itself. We do that whole path, from the register map to the board on the bench.
Because we also write Linux and bare-metal drivers and bring up embedded Linux, the logic and the software that drives it are designed together, and nothing is lost at the hand-off.
What you get
- RTL in SystemVerilog or VHDL, written for your device and your coding rules.
- Self-checking testbenches and a regression that runs from one command, each test with a forced-failure control.
- Constraints and timing closure, with clock-domain crossings found and checked.
- The design running on your board, not only in simulation.
- Scripts, not clicks: the bitstream rebuilds from a clean checkout.
- Documentation of the register map, the interfaces and the test results.
What we design
Pick one area or the whole design.
| RTL design | SystemVerilog and VHDL: AXI4 and AXI4-Lite IP, register banks, state machines, data paths and clock-domain crossings |
|---|---|
| Verification | Self-checking testbenches, regressions with negative controls, simulation in Vivado, Active-HDL or Verilator |
| High-speed I/O | PCIe, DDR3 and DDR4 memory interfaces, Gigabit and 10G Ethernet, multi-gigabit transceivers (SerDes) |
| Timing closure | Clock planning, constraints, CDC analysis and closing timing on a full device |
| Processor systems | Zynq and Versal processing system plus programmable logic, and MicroBlaze or MicroBlaze V soft processors |
| Board bring-up | First power-up of the FPGA on a new board: configuration, clocks, DDR, links and the debug to get them working |
AMD devices
The parts we design for, with Vivado and Vitis.
| Adaptive SoCs | AMD Zynq-7000, Zynq UltraScale+ MPSoC and RFSoC, and Versal adaptive SoCs |
|---|---|
| FPGAs | AMD Artix-7, Kintex, Virtex, Spartan-6 and Spartan-7 FPGAs |
Which package fits
FPGA work is sold through the same fixed-price packages as everything else. See all packages and prices.
| Package | Price | FPGA work it covers |
|---|---|---|
| Quick-Start Review | $495 | A 60-minute session on your design, timing report or board, with a written action list. Credited toward any package. |
| Bring-Up-Blitz | $10K–30K | A new FPGA or Zynq board brought up: configuration, clocks, DDR, the boot chain and a bare-metal or Linux console. |
| Driver-In-A-Box | $30K–60K | One FPGA block and its Linux or bare-metal driver, designed together: RTL, testbench, register map and driver. |
| Develop-Optimize-Deploy | From $60K | A complete FPGA design or SoC system: RTL, high-speed interfaces, timing closure, and the embedded Linux software that runs on it. |
FPGA design questions
VHDL or SystemVerilog?
Either. We write new logic in the language your team maintains, and work in mixed-language projects.
Which tools do you use?
AMD Vivado and Vitis for synthesis, implementation and the processor side; Vivado, Active-HDL or Verilator for simulation. Builds are scripted in Tcl so they run the same on any machine.
Can you write the software too?
Yes. We write the Linux kernel or bare-metal driver for the logic we design, and can bring up embedded Linux on the processing system. See driver development.
How is FPGA design priced?
Through the same fixed-price packages as the rest of our work, not by the hour. See which package fits below, or all packages and prices.
How an engagement runs
- Quick-Start Review. A 60-minute video session on your design, schematics and blockers, with a written action list. The $495 is credited toward any package.
- Fixed scope and price. You get a written scope with deliverables and one fixed price before work starts.
- Delivery. The work is done to that scope, with scripted builds and a regression.
- Handover. Source, build scripts, test results and documentation, so your team can carry on without us.
Related
Tell us about your FPGA design
No obligation. Scoping and pricing questions welcome.