VPX (ANSI/VITA 46) is the rugged backplane standard used across defense, aerospace and industrial embedded computing. ANSI/VITA 46.11 adds system management to it: a way for the chassis to discover each plug-in module, read its health and control its power. The piece of each module that does this is the Intelligent Platform Management Controller, or IPMC.
Where the IPMC sits
A VITA 46.11 system has one Chassis Manager and one IPMC on each plug-in module. They talk over the Intelligent Platform Management Bus (IPMB), an I2C-based bus that runs at 100 kHz. Every module has two of them, IPMB-A and IPMB-B, so management keeps working when one bus fails.
The IPMC is separate from the module's main processor, the payload. It runs on its own small microcontroller and stays powered from the management supply while the payload is off. That is what lets the Chassis Manager decide whether the payload should power up at all.
What the IPMC does
VITA 46.11 is built on the IPMI v2.0 message set. The IPMC answers IPMI requests from the Chassis Manager and takes care of five jobs:
- Identity. It answers Get Device ID and reports its address, worked out from the geographic address pins of the slot.
- FRU inventory. It stores the Field Replaceable Unit record: board and product names, part and serial numbers, manufacturing date. The Chassis Manager reads it and can write to it.
- Sensors. It measures supply voltages and temperatures and describes each sensor, with its units and thresholds, in Sensor Data Records (SDRs).
- FRU state and payload power. It runs the FRU state machine, from M0 (not installed) through M4 (active) to M7 (communication lost), and switches payload power on and off as the state changes.
- Events. At Tier-2 and Tier-3 it sends event messages to the Chassis Manager when a sensor crosses a threshold, and at Tier-3 it keeps a System Event Log.
Tiers
VITA 46.11 defines three tiers of capability. Tier-1 is the mandatory minimum, Tier-2 adds events and resets, and Tier-3 adds full FRU control, the event log and faster IPMB. Which tier a module needs depends on its Chassis Manager and the system around it. See VITA 46.11 Tier-1 vs Tier-2 vs Tier-3 for the details.
What the IPMC needs from the hardware
The hardware side is small: two I2C ports for IPMB-A and IPMB-B, GPIO for the geographic address straps and the payload power signals (enable, power good, fault, reset), an ADC for the supply rails, and a UART for a console. A low-cost Arm Cortex-M microcontroller is enough.
Choosing an IPMC
Many teams license IPMC firmware instead of writing it: the standard is long, and working with the Chassis Manager depends on getting its details right. When you compare options, ask:
- Which tiers does it support, and can you move from one tier to another without changing code?
- Which processors does it run on, and how much work is a port to your microcontroller?
- How was it verified? Look for conformance tests written from the standard, and for tests against a real Chassis Manager.
- How is firmware updated in the field, and does the bootloader check the image before it runs it?
- What does certification need? On avionics programs, ask about DO-178C evidence and the toolchain.
Our own answer is an IPMC written completely in Rust, covering Tier-1, Tier-2 and Tier-3 from one source tree on a single Arm Cortex-M4F. See the IronKernel IPMC.